As System-on-Chip (SoC) designs become increasingly complex, traditional security verification approaches face growing challenges in scalability, automation, and comprehensive coverage. SV-LLM introduces a multi-agent framework that uses Large Language Models (LLMs) to automate and enhance key stages of SoC security verification, including security asset identification, threat modeling, property and test-plan generation, vulnerability detection, and simulation-based validation. By combining specialized AI agents with techniques such as retrieval-augmented generation, fine-tuning, and in-context learning, the approach aims to reduce manual effort and identify security risks earlier in the design cycle. The research demonstrates how agentic AI can transform hardware security verification into a more scalable, adaptive, and proactive process.