As System-on-Chip (SoC) designs become more complex and increasingly rely on third-party IP and global supply chains, identifying security vulnerabilities before fabrication has become critical. This survey provides a comprehensive overview of state-of-the-art pre-silicon security verification techniques, examining methods used to evaluate hardware designs against potential security threats before they reach the manufacturing stage. The authors compare the key approaches, their underlying principles, strengths, and limitations, providing designers with guidance for selecting verification methods based on specific security requirements. The research highlights the growing importance of comprehensive, scalable security verification throughout the SoC design lifecycle to reduce risk and address vulnerabilities before tapeout.